Description

This 12-week live internship is designed to simulate that real-world engineering workflow.

Instead of spending weeks designing individual IPs from scratch, you will receive three pre-designed RTL IPs—just as an integration engineer would in industry. Your role is to understand the architecture, verify each IP, prepare engineering documentation, integrate the IPs into a complete AXI4-Lite subsystem, and perform system-level verification.

By the end of the internship, you will have completed a professional RTL integration project that demonstrates practical skills valued by semiconductor companies.

Final Project

RTL Subsystem Integration using AXI4-Lite

Throughout the internship, you will integrate three industry-style RTL IPs into a single memory-mapped subsystem.

The project includes:

• GPIO IP
• Timer IP
• UART TX IP
• AXI4-Lite Slave Interface
• Address Decoder
• Top-Level RTL Integration
• System-Level Verification

What You Will Receive

At the beginning of the internship, every student will receive complete RTL source code for:

• GPIO IP
• Timer IP
• UART TX IP

Each IP includes:

• RTL Source Code
• Self-Checking Testbench
• Functional Specification
• Architecture Document
• Block Diagram
• Port Table
• Register Map
• Timing Diagram
• Module Documentation
• Simulation Results
• Verification Checklist

You will work with these IPs exactly as an RTL Integration Engineer would in industry.

What You Will Learn

Rather than designing IPs from scratch, you will learn how to:

• Understand an unfamiliar RTL codebase
• Read engineering documentation
• Simulate and verify existing RTL
• Identify interfaces and register maps
• Integrate multiple RTL IPs into one subsystem
• Implement address decoding
• Connect peripherals through an AXI4-Lite interface
• Perform top-level simulation and debugging
• Create professional documentation

12-Week Internship Curriculum

Weeks 1–2: Project Orientation

• RTL Integration Flow
• Development Environment Setup
• Vivado and ModelSim
• Understanding the Project Architecture
• Introduction to AXI4-Lite
• Reading Existing RTL Code

Weeks 3–4: GPIO IP

• Understand the RTL implementation
• Run simulations
• Verify functionality
• Study the register interface
• Analyze timing diagrams
• Review the documentation

Weeks 5–6: Timer IP

• Analyze the timer architecture
• Verify counter operation
• Understand the prescaler
• Perform simulation
• Review documentation

Weeks 7–8: UART TX IP

• Study the UART transmitter
• Understand the baud-rate generator
• Analyze the FSM
• Simulate UART transmission
• Verify functionality

Weeks 9–10: RTL Integration

• GPIO IP
• Timer IP
• UART TX IP

using:

• AXI4-Lite Slave Interface
• Address Decoder
• Memory-Mapped Register Interface

Week 11: System Verification

Students will:

• Verify the complete subsystem
• Debug integration issues
• Analyze simulation waveforms
• Validate register accesses
• Perform functional testing

Week 12: Final Project

• Complete project review
• Engineering documentation
• Best practices for RTL integration
• Interview preparation
• Internship completion certificate

 

Why This Internship Is Different…

After reviewing many VLSI training programs, we found that dedicated RTL Integration training is rarely offered as a structured internship. This particular internship at RTL Labs focuses on what RTL Integration Engineers actually do:

We believe specialized RTL Integration training shouldn’t be limited by premium pricing. At RTL Labs, we’ve chosen to make this internship available at just ₹24,500, giving every engineering student access to industry-oriented training that delivers exceptional value without compromising on practical learning.